library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity total is
port(rst:in std_logic;clk:in std_logic;out1:out std_logic_vector(6 downto 0);out2:out std_logic_vector(6 downto 0);
		h:buffer std_logic_vector(3 downto 0);l:buffer std_logic_vector(3 downto 0));
end entity total;


architecture bool of total is
	component div50 is
	port(clk:in std_logic;clkout:out std_logic);
	end component div50;
	component cnt100 is
	port(rst:in std_logic;clk:in std_logic;cntout1:buffer std_logic_vector(3 downto 0);cntout2:buffer std_logic_vector(3 downto 0));
	end component cnt100;
	component decode is
	port(cntin1:in std_logic_vector(3 downto 0);cntin2:in std_logic_vector(3 downto 0);ledout1:out std_logic_vector(6 downto 0);ledout2:out std_logic_vector(6 downto 0));
	end component decode;
	
	signal clkout:std_logic;
	--signal h,l:std_logic_vector(3 downto 0);
	
begin 
	div1:div50 port map(clk,clkout);
	cnt1:cnt100 port map(rst,clkout,h,l);
	dec:decode port map(h,l,out1,out2);

end architecture bool;



